(a) Field of the Invention
The present invention relates to a semiconductor device having a multilayer wiring structure and a method of manufacturing the same and, more particularly, to a highly reliable multilayer wiring structure which is free from disconnections and variations in its electrical characteristics, and a method of forming such a multilayer wiring structure.
(b) Description of the Prior Art
When the electrode wiring area increases as in highly integrated semiconductor devices, a multilayer wiring structure must be employed. However, conventional multilayer wiring techniques have the disadvantage of disconnecting and degrading the electrical characteristics which are caused by poor step coverage, thereby deminishing the reliability of a semiconductor device.
Wiring disconnections can be eliminated by flattening a step between an insulating film and an underlying electrode wiring layer, and making uniform the thickness and stress of an overlying electrode wiring layer which crosses over the underlying electrode wiring layer. At the same time, a simple etching technique must also be proposed to etch the insulating film to form an opening having moderately inclined wall surfaces so as to obtain a complete electrical connection between the underlying and overlying electrode wiring layers.
A conventional flattening technique is proposed wherein a dispersion obtained by dispersing and dissolving fine SiO.sub.2 particles in an alcohol-based solvent is applied by a spin coater on a CVD-SiO.sub.2 or PSG (phosphosilicate glass) film formed as an insulating interlayer on an underlying electrode wiring layer. The resultant structure is annealed at a temperature of 200.degree. to 500.degree. C., thereby forming a flattened silica film.
However, in the conventional method of forming the silica film on the CVD-SiO.sub.2 or PSG film, it is difficult to obtain a silica film having a sufficient thickness to moderate the stepped portion, for example, a thickness of 0.2 to 0.3 .mu.m in a single coating step. In addition to this disadvantage, the silica film has a low mechanical stength and tends to become cracked at an opening for depositing an electrode metal due to a difference in stress between the silica film and the electrode metal at the time of annealing. As a result, the yield of the semiconductor devices and the reliability of the wiring layers are low since electrical disconnections tend to occur in the multilayer electrode structure.
Another conventional flattening technique is known wherein a polyimide-based resin which has a stress releasing property with respect to the underlying layer and high heat resistance is coated by a spin coater and is baked to form an insulating interlayer of the polyimide-based resin film with a small step, thereby obtaining a multilayer wiring structure.
This conventional method using the polyimide resin has the advantage in that the insulating interlayer of 2 to 3 .mu.m thickness required for the interlayer insulation can be applied by a single coating cycle. However, the polyimide resin has poor water-absorption resistance and humidity resistance. In particular, when a semiconductor device encapsulated in a compact plastic package is kept in operation for a long period of time, the electrical characteristics of the semiconductor elements such as a transistor formed on a substrate can vary, thus failing to assure sufficient reliability.
Still other conventional flattening techniques are also proposed. According to one technique, a part of an aluminum electrode wiring layer is subjected to anodic oxidation to flatten the electrode layer. According to another technique, after a flat organic film is applied to the surface of an inorganic insulating film, the films are sputter-etched under the conditions that both films are etched at an equal etching rates, thereby flattening the inorganic insulating film.
Any one of these conventional flattening techinques is more complicated as compared with the process wherein the silica film or the polyimide resin film is simply applied by the spin coater for forming an insulating interlayer.